Job Description

 𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲: 4–10 Years

𝗘𝗺𝗽𝗹𝗼𝘆𝗺𝗲𝗻𝘁 𝗧𝘆𝗽𝗲: Subcontract
𝐍𝐨𝐭𝐢𝐜𝐞 𝐏𝐞𝐫𝐢𝐨𝐝: Immediate to 3 Weeks

𝗥𝗼𝗹𝗲 𝗢𝘃𝗲𝗿𝘃𝗶𝗲𝘄:
We are looking for experienced SoC Verification Engineers with strong hands-on expertise in SystemVerilog / UVM and solid understanding of SoC protocols and verification methodologies.

𝗞𝗲𝘆 𝗦𝗸𝗶𝗹𝗹𝘀 𝗥𝗲𝗾𝘂𝗶𝗿𝗲𝗱
• Strong hands-on experience with SV / UVM
• Good understanding of AXI4, PCIe, Ethernet, NoC, UCIe
• Experience in testbench development & UVM test case coding
• Solid understanding of coverage closure
• Knowledge of encryption & decryption is a plus

Employment Status

Full Time

Educational Requirements

B.Tech

Experience Requirements

3 - <5 Years